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ir3622mpbf www.irf.com high frequency 2-phase, single or dual output synchronous step down controller with ou tput tracking and sequencing description the ir3622 ic integrates a dual synchronous buck controller, providing a high performance and flexible solution. the ir3622 can be configured as 2-independent outputs or as current shared single output. the current share configuration is ideal for high current applications. the ir3622 enables output tracking and sequencing of multiple rails in either ratiometric or simultaneous fashion. the ir3622 features 180 o out of phase operation which reduces the required input/output capacitance and results in lower number of capacitors. the switching frequency is programmable from 200khz to 600khz per phase using one external resistor. in addition, ir3622 also allows the switching frequency to be synchronized to an external clock signal. other key features offered by this device include two independent programmable soft starts, two independent power good outputs, precision enable input, and under voltage lockout function. the current limit is provided by sensing the lower mosfet's on-resistance for optimum cost and performance. the output voltages are monitored through dedicated pins to protect against open circuit, and enhance faster response to an overvoltage event. features ? dual synchronous controller with 180 o out of phase operation ? configurable to 2-independent outputs or current shared single output ? output voltage tracking ? power up / down sequencing ? current sharing using inductor?s dcr ? +/-1% accurate reference voltage ? programmable switching frequency up 600khz ? programmable over current protection ? hiccup current limit using mosfet r ds(on) sensing ? latched overvoltage protection ? dual programmable soft-starts ? programmable enable input ? pre-bias start-up ? dual power good outputs ? on board regulator ? external frequency synchronization ? thermal protection ? 32-lead mlpq package applications ? embedded telecom systems ? distributed point of load power architectures ? computing peripheral voltage regulators ? graphics cards ? general dc/dc converters data sheet no.pd94722 reva ordering information pkg package pin parts parts t&r desig description count per bag per reel oriantaion m ir3622mpbf 32 100 ------- m IR3622MTRPBF 32 -- -- -- -- 3000 fig a simultaneous powerup vo1 vo2 simultaneous powerdown vo1 vo2 vo1 vo2 ratiometric powerup vo1 vo2 ratiometric powerdown vin vout1 pgnd1 ldrv1 hdrv1 ldrv2 hdrv2 gnd comp2 comp1 ss1 / sd ir3622 rt ss2 / sd pgnd2 ocset2 ocset1 vin vout2 vout1 track seq 03/15/07
ir3622mpbf www.irf.com package information 2 ja = 36 o c/w * jc = 1 o c/w * exposed pad on underside is connected to a copper pad through vias for 4-layer pcb board design absolute maximum ratings (voltages referenced to gnd) vcc, vcl supply voltage ... ...................... ............? -0.5v to 16v vch1,vch2 ?????????.????.??? -0.5v to 30v pgood1, pgood2 ???. .??????????. -0.5v to 16v hdrv1, hdrv2 ???????????????? -0.5v to 30v (-2v for 100ns) ldrv1, ldrv2 ???????????????? -0.5v to 16v (-2v for 100ns) gnd to pgnd ???????????????.. +/- 0.3v storage temperature range .......... ........................ -65c to 150c operating junction temperatur e range ................ -40c to 125c esd classification ????????????..? jedec, jesd22-a114 (1kv) moisture sensitivity level ??????????.. jedec, level 3 @ 260 o c caution: stresses above those listed in ?absolute maximum rating? may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ?absolute maximum rating? conditions for extended periods may affect device reliability. e n a b l e 13 fb1 comp1 ss1/sd1 ocset1 vch1 p g n d 2 l d r v 2 v c l l d r v 1 comp2 ss2/sd2/mode ocset2 vch2 hdrv2 v ou t 3 v c c p g o o d 1 g n d 4 5 6 7 8 9 10 11 12 17 18 19 20 21 28 29 30 31 32 pad 14 15 16 pgood2 sync v sen1 22 23 24 v sen2 fb2 1 2 3 v r e f v p 2 25 26 27 p g n d 1 s e q h d r v 1 rt t r a c k v p 1
ir3622mpbf www.irf.com recommended operating conditions 3 electrical specifications unless otherwise specified, these specific ation apply over vcc=vcl=vch1=vch2=12v, 0 o c ir3622mpbf www.irf.com electrical specifications 4 parameter sym test condition min typ max units error amplifier 1, 2 fb voltage input bias current ifb ss=3v -0.1 -0.5 note1 0.4 vcc-2 v internal regulator output accuracy vout3 6.7 7.2 7.7 v dropout vdrop vcc(min)=9v, isource=100ma 2 v current limit ishort 110 ma soft start/sd soft start current iss source/sink 18 23 28 over current protection ocset current i ocset 16 20 24 note1 5 % over voltage protection ovp trip threshold ovp(trip) 1.1vref 1.15vref 1.2vref v ovp fault prop delay ovp(delay) output forced to 1.25vref 5 thermal shutdown thermal shutdown note1 140 o c thermal shutdown hysteresis note1 20 o c power good vsen lower trip point vsen(trip) vsen ramping down 0.8vref 0.9vref 0.95vref v pgood output low voltage pg(voltage) i pgood =2ma 0.1 0.5 v output drivers lo, drive rise time tr(lo) c load =3.3nf, fs=300khz, 2v to 9v 25 50 ns lo drive fall time tf(lo) c load =3.3nf, fs=300khz, 9v to 2v 25 50 ns hi drive rise time tr(hi) c load =3.3nf, fs=300khz, 2v to 9v 25 50 ns hi drive fall time tf(hi) c load =3.3nf, fs=300khz, 9v to 2v 25 50 ns dead band time tdead see figure1 20 60 100 ns seq input on 2.0 seq threshold seq off 0.3 v tracking track voltage range tk note1 0 vcc v
ir3622mpbf www.irf.com 5 note1: guaranteed by design but not tested in production. note2: cold temperature performance is guaranteed via correlation using statistical quality control. not tested in production. 9v 2v 9v 2v high side driver (hdrv) low side driver (ldrv) tr tf deadband h_to_l deadband l_to_h tr tf fig. 1: rise / fall and deadband time for driver section
ir3622mpbf www.irf.com 6 pin# pin name description 1 rt connecting a resistor from this pin to ground sets the switching frequency (see figure 16 on page 17 for selecting resistor value) 2 v sen2 sense pin for ovp2 and power good2, channel 2 3 fb2 inverting input to the error amplifier2 4 comp2 compensation pin for the error amplifier2 5 ss2/sd2/mode soft start for channel 2, can be used as sd pin. float this pin for current share single output application 6 ocset2 current limit set point for channel2 7, 17 vch2, vch1 supply voltage for the high side output drivers. these are connected to voltage that must be typically 6v higher than their bus voltages. a 0.1uf high frequency capacitor must be connected from these pins to pgnd to provide peak drive current capability 8,16 hdrv2, hdrv1 output drivers for the high side power mosfets 9 enable enable pin, recycling this pin will reset ov, ss and prebias latch 10, 14 pgnd2, pgnd1 these pins serve as the separate grounds for mosfet drivers and should be connected to the system?s ground plane 11, 13 ldrv2 , ldrv1 output drivers for the synchronous power mosfets 12 vcl supply voltage for the low side output drivers 15 seq enable pin for tracking and sequencing. if this pin is not used connect it to v out3 18 ocset1 current limit set point for channel 1 19 ss1/sd1 soft start for channel 1, can be used as sd pin 20 comp1 compensation pin for the error amplifier1 21 fb1 inverting input to the error amplifier1 22 v sen1 sense pin for ovp1 and power good1, channel 1 23 sync external synchronization pin 24 pgood2 power good pin output for channel 2, open collector. this pin needs to be externally pulled high 25 v p1 non inverting input of error amplifier1 26 v p2 non inverting input of error amplifier2 27 v ref reference voltage 28 gnd ic?s ground 29 pgood1 power good pin output for channel 1, open collector. this pin needs to be externally pulled high 30 vcc supply voltage for the internal blocks of the ic. a 0.1uf high frequency capacitor must be connected from this pin to gnd. 31 v out3 output of the internal regulator. a 0.1uf high frequency capacitor must be connected from this pin to pgnd. 32 track sets the type of power up / down sequencing (ratiometric or simultaneous). if this pin is not used connect it to v out3
ir3622mpbf www.irf.com block diagram fig. 2: simplified bloc k diagram of the ir3622 7 pbias2 bias generator ldrv2 two phase oscillator 0.8v 3v ramp1 sync gnd hdrv2 vch2 ss1 / sd comp2 error amp2 pwm comp2 por pgood2 23ua reset dom ldrv1 v cl hdrv1 vch1 fb1 comp1 error amp1 pwm comp1 reset dom set1 set2 ramp2 64ua uvlo vch2 vch1 fb2 pgnd2 vcc rt ss2 / sd v p2 v ref pgood1 r s q q s r v sen1 ocset2 ovp1 thermal shutdown pgnd1 ocset1 23ua 64ua hiccup control ss1 ss2 mode regulator mode 20ua 20ua por 0.8v pbias1 0.3v ss1 pbias1 ss1 ss2 3ua 3ua por 0.3v ss2 por v p1 tracking seq track ss1 / sd v out3 enable hdrv1 off / ldrv1 on ovp1 ovp2 1.15vref 0.90vref v sen2 ovp2 hdrv2 off / ldrv2 on q r s por 1.15vref 0.90vref vcc q r s por q r s r s q seq 23ua
ir3622mpbf www.irf.com 8 vfb1 vs temperature 0. 7975 0. 798 0. 7985 0. 799 0. 7995 0. 8 0. 8005 0. 801 0. 8015 0. 802 -40-20 020406080100120 tem perature (c) vfb1 (v) vfb2 vs temperature 0. 7975 0. 798 0. 7985 0. 799 0. 7995 0. 8 0. 8005 0. 801 0. 8015 0. 802 -40 -15 10 35 60 85 110 temperature (c) vfb2 (v) ss1 current vs temperature -25 -24 -23 -22 -21 -20 -19 -40 -15 10 35 60 85 110 temperature (c) ss1 current (ua) ss2 current vs temperature -25 -24 -23 -22 -21 -20 -19 -40 -15 10 35 60 85 110 tem perature (c) ss2 current (ua) vcc_uvlo vs temperature 7.1 7.12 7.14 7.16 7.18 7.2 7.22 7.24 7.26 7.28 7.3 -40 -15 10 35 60 85 110 tem perature (c) vcc_uvlo (v) vout3 vs temperature 7. 05 7. 07 7. 09 7. 11 7. 13 7. 15 7. 17 7. 19 7. 21 7. 23 7. 25 -40 -15 10 35 60 85 110 temperature (c) vout3 (v) typical operating characteristics (-40 o c-125 o c)
ir3622mpbf www.irf.com 9 iocset1 vs temperature 19 19.5 20 20.5 21 21.5 22 -40 -15 10 35 60 85 110 tem perature (c) iocset1 (ua) iocset2 vs temperature 18 18. 5 19 19. 5 20 20. 5 21 21. 5 22 -40 -15 10 35 60 85 110 temperature (c) iocset2 (ua) gm1 vs temperature 3400 3500 3600 3700 3800 3900 4000 -40 -15 10 35 60 85 110 temperature (c) gm1 (umho) gm2 vs temperature 3400 3500 3600 3700 3800 3900 4000 4100 -40 -15 10 35 60 85 110 temperature (c) gm2 (umho) freq 300khz vs temperature 280 290 300 310 320 -40 -15 10 35 60 85 110 tem perature (c) freq (khz) max duty cycle vs temperature 84 86 88 90 92 94 96 -40 -15 10 35 60 85 110 tem perature max duty cycle (%) typical operating characteristics (-40 o c-125 o c)
ir3622mpbf www.irf.com circuit description 10 theory of operation introduction the ir3622 is a versatile device for high performance buck converters. it consists of two synchronous buck controllers which can be operated either in two independent outputs mode or in current share single output mode for high current applications. the timing of the ic is provided by an internal oscillator circuit which generates two 180 o -out-of- phase clock signals that can be externally programmed up to 600khz per phase. under-voltage lockout the under-voltage lockout circuit monitors four signals (vcc, vch1, vch2 and enable). this ensures the correct operation of the converter during power up and power down sequence. the driver outputs remain in the off state whenever one of these signals drop below set thresholds. normal operation resumes once these signals rise above the set values. figure 3 shows a typical start up sequence. programmable enable input the enable features another level of flexibility for start up. the enable has precise threshold which is internally monitored by under-voltage lockout circuit. it?s threshold can be externally programmed to desired level by using two external resistors, so the converter doesn?t start up until the input voltage is sufficiently high (see figure 3). vcc 7.2v vout3 enable vbus 7.2v 11v 12v 12v ss 3v enable ok (ic's por) seq fig. 3: normal start up, enable threshold is externally set to 11v seq pin is pulled to vout3 prior to start up
ir3622mpbf www.irf.com 11 internal regulator the ir3622 features an on-board 7.2v regulator with short circuit protection. the regulator is capable of sourcing current up to 100ma. this integrated regulator can be used to generate the necessary bias voltage for drivers, an example of how this can be used is shown in figure 23, page26. out-of-phase operation the ir3622 drives its two output stages 180 o out- of-phase. in current share mode single output, the two inductor ripple currents cancel each other and result in a reduction of the output current ripple and yield a smaller output capacitor for the same voltage ripple requirement. figure 4 shows two channels inductor current and the resulting voltage ripple at the output. il1 il2 hdrv1 hdrv2 0dt t ic io mode selection the ir3622 can operate as a dual output independently regulated buck converter, or as a 2 phase single output buck converter (current share mode). the ss2 pin is used for mode selection. in current share mode this pin should be floating. in the dual output mode, a soft start capacitor must be connected from this pin to the ground to program the start time for the second output. independent mode in this mode the ir3622 provides control to two independent output power supplies with either common or different input voltages. the output voltage of each individual channel is set and controlled by the output of the error amplifier, which is the amplified error signal from the sensed output voltage and the reference voltage. the error amplifier output voltage is compared to the ramp signal thus generating fixed frequency pulses of variable duty-cycle, (pwm) which are applied to the internal moseft drivers. figure 24 shows a typical schematic for such application. fig. 4: current ripple cancellation for output in addition, the 180 o out of phase contributes to input current cancellation. this results in much smaller input capacitor?s rms current and reduces the number of required input capacitors. figure 5 shows the equivalent rms current. single phase 2 phase duty cycle (vo/vin) rms current normalized (i rms /i out ) fig. 5: input rms value vs. duty cycle
ir3622mpbf www.irf.com 12 current share mode this feature allows to connect both outputs together to increase curr ent handling capability of the converter to support a common load. in the current sharing mode, error amplifier 1 becomes the master which regulates the common output voltage and the error amplifier 2 performs the current sharing function, figure 6 shows the configuration of error amplifier 2. in this mode, ir3622 makes sure the master channel starts first followed by slave channel to prevent any glitch during start up. this is done by clamping the output of slave?s error amplifier until the master channel generates the first pwm signal. at no load condition the slave channel may be kept off depending on the offset of the error amplifier. lossless inductor current sensing the ir3622 uses a lossless current sensing for current share purposes. the inductor current is sensed by connecting a series resistor and a capacitor network in parallel with the inductor and by measuring the voltage across the capacitor. the measured voltage is proportional to the inductor current. this is shown figure 6. the voltage across the inductor?s dcr can be expressed by: the voltage across the c 1 can expressed by: combining equations (1),(2) and (3) result in the following expression for v c1 : usually the resistor r 1 and c 1 are chosen so that the time constant of r 1 and c 1 equals the time constant of the inductor which is the inductance l 1 over the inductor?s dcr (r l1 ). if the two time constants match, the voltage across c 1 is proportional to the current through l 1 , and fig. 6: loss less inductor current sensing and current sharing l1 r l1 r1 l2 r l2 r2 c2 vp2 fb2 c1 v out master phase slave phase q2 q3 q4 + v c1 (s) - + v l1 (s) - v in v in il1 the sense circuit can be treated as if only a sense resistor with the value r l1 was used. the mismatch of the time constant does not affect the measurements of inductor dc current, but affects the ac component of the inductor current. soft-start the ir3622 has programmable soft-start to control the output voltage rise and limit the inrush current during start-up. it provides a separate soft-start function for each output. this will enable to sequence the outputs by controlling the rise time of each output through selection of different value soft-start capacitors. to ensure correct start-up, the soft-start sequence initiates when the vcc, vch1, vch2 and enable rise above their threshold and generate the power on reset (por) signal. soft-start function operates by sourcing an internal current to charge an external capacitor to about 3v. initially, the soft-start function clamps the error amplifier?s output of the pwm converter. ) 1 ( - - - - sl r r v v s v 1 1 l 1 l out in 1 rl + ? = ) 2 ( - - - - r i s v 1 l 1 l 1 rl * ) ( = ) 3 ( - - - - sc 1 r sc 1 v v s v 1 1 1 out in 1 c + ? = ) 4 ( - - - - c sr 1 sl r i s v 1 1 1 1 l 1 l 1 c * * ) ( + + = 1 l 1 l c 1 l 1 1 1 r i s v r l c r if * ) ( * : =
ir3622mpbf www.irf.com soft-start (cont.) during power up, the converter output starts at zero and thus the voltage at fb is about 0v. an internal voltage-controlled current source (64ua) injects current into the fb pin and generates a voltage about 1.6v (64ux25k) across the negative input of error amplifier, see figure 7. this keeps the output of the error amplifier low. the magnitude of this current is inversely proportional to the voltage at the soft-start pin. the 23ua current source starts to charge up the external capacitor. in the mean time, the soft- start voltage ramps up, the current flowing into fb pin starts to decrease linearly and so does the voltage at the negative input of error amplifier. when the soft-start voltage reaches about 1v, the voltage at the negative input of the error amplifier is approximately 0.8v. as the soft-start capacitor voltage charges up, the current flowing into the fb pin keeps decreasing. the feedback voltage increases linearly as the injecting current goes down. the injecting current drops to zero when soft-start voltage is around 1.8v and the output voltage goes into steady state. figure 8 shows the theoretical operational waveforms during soft-start. the output start-up time is the time period when soft-start capacitor voltage increases from 1v to 1.8v. the start-up time will be dependent on the size of the external soft-start capacitor. the start- up time can be estimated by: for a given start up time, the soft-start capacitor (nf) can be estimated as: for normal start up the seq pin should be pulled high (usually can be connected to vout3). fig. 7: soft-start circuit for ir3622 fig. 8: theoretical operation waveforms during soft-start ) 5 ( - - - - v 8 0 ms t a 23 c start ss ) ( . ) ( * ) ( ? v 1 v 8 1 c t a 23 ss start ? = ? ? ? ?
ir3622mpbf www.irf.com 14 fig. 10: ratiometric power up / down output voltage tracking and sequencing the ir3622 can accommodate a full spectrum of user programmable tracking and sequencing options using track, seq, enable and power good pins. through these pins both simple voltage tracking such as that required by the ddr memory application or more sophisticated sequencing such as ratiometric or simultaneous can be implemented. the seq pin controls the internal current sources to set the power up or down sequencing. toggle this pin high for power up, and toggle this pin low for power down. the track pin is used to determine the second channel output for either ratiometric or simultaneous by using two external resistors. figure 9 shows how these pins are configured for different sequencing mode. e/a2 vp2 fb2 ss2/sd2 i ss2 = 23ua track por ocp2 i hiccup2 = 3ua 64ua 3v floating v o2 v o1 r c r d r e r f vref e/a1 vp1 fb1 ss1/sd1 i ss1 = 23ua por ocp1 i hiccup1 = 3ua 64ua 3v seq v ref v o1 r a r b c ss1 fig. 9: using seq and track pin for different sequencing in general the r a and r b set the output voltage for the first output and r c and r d set the output voltage for the second output. for simultaneous vs. ratiometric, re and rf can be selected according to the table below: fig. 11: simultaneously power up /down simultaneously ratiometric track pin r e =r c , r f =r d r e =r a , r f =r b
ir3622mpbf www.irf.com fault protection the ir3622 monitors the output voltage for over voltage protection and power good indication. it senses the r ds(on) of low side mosfet for over current protection. it also protects the output for prebias conditions. figure 12 shows the ic?s operating waveforms under different fault conditions. 15 t 0 ?t 1 : vcc, vch1,vch2 and enable signals passed their respective uvlo threshold. soft start sequence starts. t 1 ?t 2 : power good signal flags high. t 1 ?t 3 : output voltage ramps up and reaches the set voltage. t 4 ?t 5 : oc event, ss ramps down. ic in hiccup mode. t 5 ?t 6 : oc is removed, recovery sequence, fresh ss. t 6 ?t 7 : output voltage reaches the set voltage. t 8 : ovp event. hdrv turns off and ldrv turns on. the ic latches off. t 9 ?t 10 : manually recycled the vcc after latched ovp. prebias start up. t 10 ?t 11 : new soft start sequence fig. 12: fault conditions ss pgood t 1 t 2 t 3 vo 1.0v 1.8v 90%vfb set voltage ocp threshold iout 3v por t 0 t 4 t 5 t 6 t 7 t 8 t 10 t 11 pre_bias voltage ov t 9
ir3622mpbf www.irf.com over-current protection the over current protection is performed by sensing current through the r ds(on) of the low side mosfet (q2). this method enhances the converter?s efficiency and reduce cost by eliminating a current sense resistor. as shown in figure 13, an external resistor (r set ) is connected between the ocset pin and the drain of q2 which sets the current limit set point. the internal current source develops a voltage across r set . when the q2 is turned on, the inductor current flows through the q2 and results in a voltage drop which is given by: the ocp circuit starts sampling current when the low gate drive is about 3v. the ocset pin is internally clamped to approximately 1.4v during deadtime to prevent false trigging. figure 15 shows the ocset pin during one switching cycle. there is about 150ns delay to mask out the deadtime, since this node contains switching noise, this delay also functions as a filter. fig. 13: connection of over current sensing resistor fig. 14: 3ua current source for discharging soft-start capacitor during hiccup an over current is detected if the ocset pin goes below ground. this trips the ocp comparator and cycles the soft start function in hiccup mode. the hiccup is performed by charging and discharging the soft-start capacitor at a certain slope rate. as shown in figure 14 the 3ua current source is used to discharge the soft-start capacitor. the ocp comparator resets after every soft start cycles, and the converter stays in this mode until the overload or short circuit is removed. the converter will automatically recover. ss1 / sd 20 28ua 3ua ocp ) 6 ( - - - - ) i (r ) r (i v l ds(on) ocset ocset ocset ? ? ? = 0 ) i (r ) r (i v l ds(on) ocset ocset ocset = ? ? ? = ) 7 ( - - - - r i r i i on ds ocset ocset critical l set ) ( ) ( ? = =
ir3622mpbf www.irf.com 17 pre-bias the ir3622 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. the output starts in asynchronous fashion and keeps the synchronous mosfet off until the first gate signal for control mosfet is generated. figure below shows a typical pre-bias condition at start up. depending on system configuration, specific amount of output capacitance may be required to prevent discharging the output voltage. over voltage protection over-voltage is sensed through two dedicated sense pins v sen1 , v sen2 . a separate ovp circuit is provided for each channel. the ovp threshold is user programmable and can be set by two external resistors. upon over- voltage condition of either one of the outputs, the ovp forces a latched shutdown on the fault output. in this mode, the upper fet driver turns off and the lower fet drivers turn on, thus crowbaring the output. reset is performed by recycling the vcc or enable. power good the ir3622 provides two separate open collector power good signals which report the status of the outputs. the outputs are sensed through the two dedicated v sen1 and v sen2 pins. once the ir3622 is enabled and the outputs reach the set value (90% of the vout set point) the power good signals go open and stay open as long as the outputs stay within the set values. these pins need to be externally pulled high. shutdown using soft start pins the outputs can be shutdown by pulling the soft- start pins below 0.3v. this can be easily done by using an external small signal transistor. during shutdown both mosfet drivers will be turned off. normal operation will resume by cycling soft start pin. fig. 16: switching frequency vs. external resistor (r t ) operating frequency selection the switching frequency is determined by connecting an external resistor (rt) to ground. figure 16 provides a graph of oscillator frequency versus rt. the maximum recommended channel frequency is 600khz. frequency synchronization the ir3622 is capable of accepting an external digital synchronization signal. synchronization will be enabled by the rising edge at an external clock. per ?channel switching frequency is set by external resistor (rt). the free running frequency oscillator frequency is twice the per- channel frequency. during synchronization, rt is selected such that the free running frequency is 20% below the synchronization frequency. synchronization capability is provided for both single output current share mode and dual output configuration. the sync pin is noise immune, when unused it should be left floating. thermal shutdown temperature sensing is provided inside ir3622. the trip threshold is typically set to 140 o c. when trip threshold is exceeded, thermal shutdown turns off both mosfets. thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to the normal range. there is a 20 o c (typical) hysteresis in the shutdown threshold. vo time v pre-bias voltage (output voltage before startup) 0 100 200 300 400 500 600 700 5 101520253035404550556065 rt (kohm) fsw (khz)
ir3622mpbf www.irf.com application information design example: the following is a design of typical single output current share application for ir3622. the application circuit is shown on page 26. output voltage programming output voltage is programmed by reference voltage and external voltage divider. as shown in figure 17 the fb1 pin is the inverting input of the error amplifier, which is internally referenced to 0.8v. the divider is set to provide 0.8v at the fb pin when the output is at its desired value. the output voltage is defined by the following equation: equation (8) can be rewritten as: for the calculated values of r 5 and r 6 see feedback compensation section. khz 375 f mv 30 v a 40 i v 8 1 v 10 v 12 v s o o o in = = = = ? ) 8 ( - - - - r r 1 v v 5 6 ref o ? ? ? ? ? ? ? ? + ? = ) 9 ( - - - - v v v r r ref o ref 6 5 ? ? ? ? ? ? ? ? ? ? = soft-start programming the soft-start timing can be programmed by selecting the soft-start capacitance value. the start-up time of the converter can be calculated using the following expression: where t start is the desired start-up time (ms) for a start-up time of 5ms, the soft-start capacitor will be 0.15uf. choose a ceramic capacitor at 0.15uf. input capacitor selection the 180 o out of phase will reduce the rms value of the ripple current seen by input capacitors. this reduces numbers of input capacitors. the input capacitors must be able to handle both the maximum ripple rms current at the highest ambient temperature, as well as the maximum input voltage. the rms value of current ripple for a duty cycle under 50% is expressed by: where: -i rms is the rms value of the input capacitor current -d 1 and d 2 are duty cycle for each channel -i 1 and i 2 are the output current for each channel for io=40a and d=0.16 (1.8v/10.8v), the i rms = 9.43a. ceramic capacitors are recommended due to their peak current capabilities. they also feature low esr and esl at higher frequency, which enhance circuit efficiency. use 10x22uf, 16v ceramic capacitor from tdk (c3225x5r1c226m). for the single output application when the duty cycle is larger than 50% the following equation can be used to calculate the total rms current for the input capacitor current: ( ) ( ) ( ) ) 10 ( - - - - ms t a 75 28 nf c start ss * . ? ( ) ( ) ( ) ) 11 ( - - - - d d i i 2 d 1 d i d 1 d i i 2 1 2 1 2 2 2 2 1 1 2 1 rms ? ? + ? = ( ) ( ) ( ) 0.5 d d 2 2 d 1 d 2 i i o rms > ? + ? =
ir3622mpbf www.irf.com inductor selection the inductor is selected based on output power, operating frequency and efficiency requirements. low inductor value results in large ripple current, smaller size, faster response to a load transient but poor efficiency and high output noise. generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor . the optimum point is usually found between 20% and 50% ripple of the output current. for the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: where: for 2-phase single output application the inductor ripple current is chosen between 20-50% of maximum phase current if , then the output inductor will be: l = 0.41uh the coilcraft mlc1260-401ml (l 1 =0.4uh, 20a, r l1 =0.93mohm) is a low profile inductor suitable for this application. use the following equation to calculate c 1 and r 1 for current sensing: (refer to figure 6 on page 12) this results to c 1 =1uf and r 1 =0.432k s o in f 1 d t t i l v v ? = ? = ? ? ? ? i ? () ) 12 ( - - - - f i v v v v l s in o o in * ? ? ? ? = cycle duty d time on turn t frequency switching f current ripple inductor i voltage output v voltage input maximum v s o in = = = = = = ? ? output capacitor selection the voltage ripple and transient requirements determine the output capacitors types and values. the criteria is normally based on the value of the equivalent series resistance (esr). however the actual capacitance value and the equivalent series inductance (esl) are other contributing factors. the overall output voltage ripple can be expressed as: therefore it is recommended to select output capacitor with low enough esr to meet output ripple and step load transient requirements. the output ripple is highest at maximum input voltage since increases with input voltage. special polymer capacitors offers low esr with large storage capacity per unit volume. these capacitors offer a cost effective output capacitor solution and are ideal choice when combined with a controller having high loop bandwidth. the ir3622 can perform well with all types of capacitors. panasonic eefsxod221r (sp, 220f, 2v, 9mohm) is selected for this design. equation (13) can be used to calculate the required esr for the specific voltage ripple. four sp capacitors would meet the voltage ripple requirement. ) %( o i 50 i ? current ripple inductor i ripple voltage output v f c 8 i v esl l v v -(13) - - - esr i v : where v v v v l o s o l c o in esl o l esr o c o esl o esr o o = = = ? ? ? ? ? ? = = + + = ? ? ? ? ? ? ? ? ? ? ? 1 l 1 1 1 r l c r = i ?
ir3622mpbf www.irf.com 20 power mosfet selection the ir3622 uses two n-channel mosfets per channel. the selection criteria to meet power transfer requirements are based on maximum drain-source voltage (v dss ), gate-source drive voltage (v gs ), maximum output current, on- resistance r ds(on) , and thermal management. the mosfet must have a maximum operating voltage (v dss ) exceeding the maximum input voltage (v in ). the gate drive requirement is almost the same for both mosfets. logic-level transistor can be used and caution should be taken with devices at very low gate threshold voltage (v gs ) to prevent undesired turn-on of the complementary mosfet, which results a shoot-through current. the total power dissipation for mosfets includes conduction and switching losses. for the buck converter the average inductor current is equal to the dc load current. the conduction loss is defined as: the r ds(on) temperature dependency should be considered for the worst case operation. this is typically given in the mosfet data sheet. ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. for this design, irf6622 is selected for control fet and irf6629 is selected for synchronous fet. these devices provide low on resistance in a compact direct fet package. the mosfets have the following data: the conduction losses will be: p con =1.1w/phase the switching loss is more difficult to calculate, even though the switching transition is well understood. the reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turn- off delays and rise and fall times. the control mosfet contributes to the majority of the dependency e temperatur r d) (1 r i switch) (lower p d r i switch) (upper p ds(on) ds(on) 2 load cond ds(on) 2 load cond = ? ? ? ? = = ? ? ? = = ? ? ? v 10 v m ? 3 . 6 r v 10 nc 7 . 18 v,q 25 v : (irf6622) controlfet gs ds(on) gs g ds = = = = p sw =2.8w the reverse recovery loss is also another contributing factor in control fet switching losses. this is equivalent to extra current requires to remove the minority charges from synchronous fet. the reverse recovery loss can be expressed as: (13a ) - - - i t t t 2 v p load f r off ds sw * * ) ( + = v 10 v m ? 1 2 r v 10 nc 51 v,q 25 v : (irf6629) syncfet gs ds(on) gs g ds = = = = frequency switching f time recovery reverse t charg e recovery verse q f t q p s rr rr s rr rr qrr : : re : * * =
ir3622mpbf www.irf.com feedback compensation the ir3622 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. to achieve fast transient response and accurate output regulation, a compensation circuit is necessary. the goal of the compensation network is to provide a closed loop transfer function with the highes t 0db crossing frequency and adequate phase margin (greater than 45 o ). the output lc filter introduces a double pole, ? 40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o (see figure 19). the resonant frequency of the lc filter expressed as follows: figure 19 shows gain and phase of the lc filter. since we already have 180 o phase shift just from the output filter, the system risks being unstable. the ir3622?s error amplifier is a differential-input transconductance amplifier. the output is available for dc gain control and ac phase compensation. the e/a can be compensated either in type ii or type iii compensation. when it is used in type ii compensation the transconductance properties of the e/a become evident and can be used to cancel one of the output filter poles. this will be accomplished with a series rc circuit from comp pin to ground as shown in figure 20. this method requires that the output capacitor has enough esr to satisfy stability requirements. in general the output capacitor?s esr generates a zero typically at 5khz to 50khz which is essential for an acceptable phase margin. the esr zero of the output capacitor expressed as follows: -(14 ) - - - c l 2 1 f o o lc ? ? = f lc -180 frequency frequency -40db/decade fig. 19: gain and phase of lc filter the transfer function (ve/vo) is given by: the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: the gain is determined by the voltage divider and e/a?s transconductance gain. first select the desired zero-crossover frequency (fo): use the following equation to calculate r 4 : where: v in = maximum input voltage v osc = oscillator ramp voltage f o = crossover frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter g m = error amplifier transconductance -(15 ) - - - c esr 2 1 f o esr * * ? = -(16 ) - - - sc c sr 1 r r r g s h 9 9 4 6 5 5 m + ? ? ? ? ? ? ? ? + = () [] -(18) - - - c r 2 1 f -(17 ) - - - r * r r r g s h 9 4 z 4 6 5 5 m * * * = ? ? ? ? ? ? ? ? + = ( ) s o esr o f 1/10 ~ 1/5 f and f f * > -(19 ) - - - g r f v r r f f v r m 5 2 lc in 6 5 esr o osc 4 * * * ) ( * * * + =
ir3622mpbf www.irf.com to cancel one of the lc filter poles, place the zero before the lc filter resonant frequency pole: using equations (18) and (20) to calculate c9. one more capacitor is sometimes added in parallel with c 9 and r 4 . this introduces one more pole which is mainly used to suppress the switching noise. the additional pole is given by: the pole sets to one half of switching frequency which results in the capacitor c pole : for a general solution for unconditional stability for any type of output capacitors in a wide range of esr values, we should implement local feedback with a compensation network (typeiii). the typically used compensation network for voltage-mode controller is shown in figure 21. in such configuration, the transfer function is given by: the error amplifier gain is independent of the transconductance under the following condition: by replacing z in and z f according to figure 15, the transformer function can be expressed as: -(20) - - - c l 2 1 75 0 f f 75 f o o z lc z * * . % = = c c c c r 2 1 f pole 9 pole 9 4 p + = 2 f f for f r * 1 c 1 f r 1 c s p s 4 9 s 4 pole << ? ? = in m f m o e z g 1 z g 1 v v + ? = ( ) [] 10 8 12 11 12 11 7 8 6 10 11 7 12 11 6 c sr 1 c c c c sr 1 r r sc 1 c sr 1 c c sr 1 s h + ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + + + = 6 10 8 6 10 2 z 11 7 1 z 12 7 12 11 12 11 7 3 p 10 8 2 p 1 p r c 2 1 r r c 2 1 f c r 2 1 f c r 2 1 c c c c r 2 1 f c r 2 1 f 0 f * * ) ( * * * * * * * * * * ? + = = ? ? ? ? ? ? ? ? ? + = = = o o osc in 10 7 o c l 2 1 v v c r f * * * * * = -(21) - - - 1 z * g and 1 z * g in m f m >> >> f r 2 1 c z 4 9 * * =
ir3622mpbf www.irf.com based on the frequency of the zero generated by output capacitor and its esr versus crossover frequency, the compensation type can be different. the table below shows the compensation types and location of crossover frequency. the following design rules will give a crossover frequency approximately one-sixth of the switching frequency. the higher the band width, the potentially faster the load transient response. the dc gain will be large enough to provide high dc-regulation accuracy (typically -5db to -12db). the phase margin should be greater than 45 o for overall stability. ceramic f lc = > = = ? = = = ? = = = = = = = = = = = = = = = = ? ? ? ? ? ? ? ? ? ? f lc =12khz (replace l to l/2 in formula#14 for current share configuration) f esr =80.38khz f s/2 =185khz select crossover frequency: f o =60khz since: f lc ir3622mpbf www.irf.com compensation for current loop (slave channel) the slave error amplifier is differential transconductance amplifier, in 2-phase configuration the main goal for the slave channel feedback loop is to control the inductor current to match the master channel inductor current as well provides highest bandwidth and adequate phase margin for overall stability. the following analysis is valid for both using external current sense resistors and using dcr of the inductor. the transfer function of power stage is expressed by: where: v in =input voltage l 2 =output inductor v osc =oscillator peak voltage as shown the g(s) is a function of inductor current. the transfer function for compensation network is given by equation (23), when using a series rc circuit as shown in figure22. the loop gain function is: 24 ) 22 ( - - - - v sl v v s i s g osc 2 in e 2 l * ) ( ) ( = = ) 23 ( - - - - sc r sc 1 r r g r s v s t 2 2 2 2 s 1 s m 2 s e ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = = [ ] 2 s r s t s g s h * ) ( * ) ( ) ( = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = osc 2 in 2 2 2 2 s 1 s m 2 s v sl v sc c sr 1 r r g r s h * * * * * ) ( select a zero frequency for current loop (f o2 ) 1.2 times larger than zero cross frequency for voltage loop (f o1 ). from (24), r2 can be expressed as: v in =13.2v v osc =1.25v g m =3000umoh l 2 =0.4uh r s1 =dcr=0.930mohm f o2 =72khz this results to : r 2 =6.14k select r 2 =6.09k the power stage of current loop has a dominant pole (fp) at frequency expressed by: where r ds(on1) is the on-resistance of control fet, r ds(on2) is the on-resistance of synchronous fet, r l is the dcr of output inductance and d is the duty cycle r eq =3.7mohm set the zero of compensator at 10 times the dominant pole frequency f p , the compensator capacitor, c2 can be expressed as: c 2 =1.8nf all design should be tested for stability to verify the calculated values. 1 o 2 o f 25 1 f * % . ? ) 24 ( - - - - 1 v l f 2 v r r g f h osc 2 2 o in 2 1 s m 2 o = = ) 25 ( - - - - v v l f 2 r g 1 r in osc 2 2 o 1 s m 2 * * * * * = l 2 r f 2 eq p * = l 2 on ds 1 on ds eq r d 1 r d r r + ? + = z 2 2 p z f r 2 1 c f 10 f * * * = =
ir3622mpbf www.irf.com programming the current-limit the current-limit threshold can be set by connecting a resistor (r set ) from drain of low side mosfet to the ocset pin. the resistor can be calculated by using equation (7). the r ds(on) has a positive temperature coefficient and it should be considered for the worse case operation. this resistor must be placed close to the ic, place a small ceramic capacitor from this pin to ground for noise rejection purposes. ? ? ? k 4 r r r current) output nominal over (50% a 30 5 1 a 20 i i m 15 3 5 1 m 1 2 r 4 3 ocset lim o set on ds = = = = ? = ? = ? = ) 7 ( - - - - r i r i i on ds ocset ocset critical l set ) ( ) ( ? = = layout consideration the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. start to place the power components, make all the connection in the top layer with wide, copper filled areas. the inductor, output capacitor should be close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place input capacitor close to control fets, to reduce the esr replace the single input capacitor with two parallel units. the feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the ic. in multilayer pcb use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. the exposed pad of ic should be connected to analog ground.
ir3622mpbf www.irf.com 26 fig. 23: application circ uit for 12v to 1.8v @ 40a 26 typical application 12v pgood1 q5 l4 q4 c5 u1 vout r8 c16 l3 c17 r9 r7 c10 r4 c9 r3 c8 c3 c4 c13 c11 pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood1 v ref ir3622 q3 q2 c14 sync rt enable ss2 / sd pgnd2 ocset2 ocset1 v sen1 v sen2 r2 r1 r6 d1 c12 c18 r5 c15 r14 r13 v p1 track seq pgood2 vout3 r10 vout3 r12 r11
ir3622mpbf www.irf.com 27 fig. 24: application circui t for dual output application tracking and sequencing using track pin 27 typical application c10 c3 12v pgood1 q5 l4 q4 c5 u1 vout1 c16 l3 r7 c4 c13 c11 pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p1 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood1 v ref ir3622 q3 q2 c14 sync rt enable ss2 / sd pgnd2 ocset2 ocset1 v sen1 r2 r1 r6 d1 bat54s c12 c15 vout2 r9 r5 r8 c18 c17 r20 r21 v sen1 v sen1 r22 r23 v sen2 v sen2 v sen2 v p2 track seq pgood2 pgood2 d2 bat54s v out3 c30 ra rb vout1 r3 c8 r4 c9 r24 v out3 r25 r26 r27 simultaneously ratiometric track pin r a =r 9 , r b =r 5 r a =r 7 , r b =r 8
ir3622mpbf www.irf.com 28 pcb metal and components placement ? lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be ? lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to maximum part pad length and width. however, the minimum metal to metal spacing should be ? a single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the ic.
ir3622mpbf www.irf.com 29 solder resist ? the solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pu lling the s/r 0.06mm will always ensure nsmd pads. ? the minimum solder resist width is 0.13mm. at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ? the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ? ensure that the solder resist in-between the lead lands and the pad land is ? the single via in the land pad should be tented or plugged from bottom boardside with solder resist.
ir3622mpbf www.irf.com 30 stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposit ed will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. ? the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. ? the land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste.
ir3622mpbf www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 this product has been designed and qualified for the industrial ma rket. visit us at www.irf.com for sales contact information data and specifications subject to change without notice. 6/15/2007 (ir3622m) mlpq package; 5x5-32 lead 3131 feed direction figure a

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